1. Field of the Invention
The present invention relates generally to data storage and more particularly to an improved structure for a conductive line connected to a Magnetic Tunnel Junction (MTJ) of a Magnetic Random Access Memory (MRAM) cell.
2. Description of the Prior Art
A wide range of presently available media for data storage vary in several attributes including access speed, duration of reliable storage, and cost. Static Random Access Memory (SRAM) is the storage medium with the best access speed for the cost in applications such as cache memories. However, SRAM is volatile, meaning that it only maintains storage while power is continuously applied. Accordingly, computer users endure lengthy waits when they power-up their computers while substantial amounts of data are written from non-volatile but slow media, such as magnetic disks, into much faster random access memory (e.g., SRAM).
Flash memory is a solid-state storage medium that provides moderate access times and that is non-volatile. Flash memory has the disadvantage that it has a limited lifetime, on the order of one million cycles per cell, after which a cell can no longer be written to. This lifetime is orders of magnitude too short for a random access memory in most modern computing system.
Another solid-state storage medium is Magnetic Random Access Memory (MRAM), which employs a Magnetic Tunnel Junction (MTJ) formed of layers of magnetic material and an insulating barrier. FIG. 1 shows a cross-section of a prior art MRAM cell 10 including an MTJ 12 formed of a pinned layer 14 and a free layer 16, which are magnetic layers typically formed of ferromagnetic materials, and a thin dielectric layer 18 disposed between layers 14 and 16. Pinned layer 14 has a magnetic moment orientation 20 that is fixed from rotating, while free layer 16 has a magnetic moment orientation 22 that is free to rotate in response to applied magnetic fields. Methods of pinning a pinned layer 14 are well known in the art and include the use of an adjacent antiferromagnetic layer 24.
In an MRAM unit 10, a bit of data is encoded in the direction of the magnetic moment orientation 22 of the free layer 16 relative to the magnetic moment orientation 20 of the pinned layer 14. As is well known in the art, when the two magnetic moment orientations 20 and 22 are parallel the resistance measured across the MTJ 12 is relatively low, and when the two magnetic moment orientations 20 and 22 are antiparallel the resistance measured across the MTJ 12 is relatively high. Accordingly, one can determine whether the magnetic moment orientations 20 and 22 are parallel or antiparallel by reading the resistance across the MTJ 12 with a read current. Typical read currents are on the order of 1-50 xcexcA.
In an MRAM unit 10, the state of the bit, parallel or antiparallel, is varied by applying a write current IW, typically on the order of 1-25 mA, through two conductors, a bit line 28 and a digit line 26, situated proximate to the MTJ 12. The bit line 28 and the digit line 26 cross one another at approximately right angles above and below the MTJ 12. As is well known in the art, although the pinned layer 14 is depicted in FIG. 1 as nearer to the bit line 26, an MRAM cell 10 also functions with the pinned layer 14 nearer to the digit line 28.
As is well known, a magnetic field develops around an electric current in a wire. Accordingly, two magnetic fields arise when write currents IW are simultaneously applied to both the bit line 28 and the digit line 26. The two magnetic fields combine at the free layer 16 to influence the magnetic moment orientation 22. The magnetic moment orientation 22 of the free layer 16 is changed between the parallel and antiparallel states by changing the direction of the write current 1W in either the bit line 28 or the digit line 26. Changing (by a write control circuit, not shown) the direction of the write current IW in one of the lines 26 or 28 reverses the direction of the magnetic field around that conductor and thereby reverses the direction of the combined magnetic field at the free layer 16.
In an MRAM unit 10, the state of the bit is read by passing a read current IR through the MTJ 12. The bit line 28 is used to conduct the read current IR to the MTJ 12. In some embodiments a transistor (not shown) is used to allow the read current IR to flow from the bit line 28 through the MTJ 12 and out through a bottom lead 25 during a read operation while preventing the write current IW from flowing through the MTJ 12 during a write operation. An insulating spacer 27 is disposed between the bottom lead 25 and the digit line 26 to prevent shorting between the two.
FIG. 2 shows a cross-section of an array 30 of MRAM cells 10 of the prior art. A line 1xe2x80x941 shows the orientation of the cross-section shown previously in FIG. 1. FIG. 2 illustrates three MRAM cells 10 connected to one bit line 28. An array 30 can include any number of MRAM cells 10 on a single bit line 28. Similarly, there can also be any number of MRAM cells 10 associated with each digit line 26 arranged in a line extending perpendicularly to the plane of the drawing. Accordingly, an array 30 typically consists of a lattice of digit lines 26 and bit lines 28, with an MRAM cell 10 at each point of intersection between the bit lines 28 and the digit lines 26. In order to affect a particular MRAM cell 10, control circuitry (not shown) is used to select the appropriate bit line 28 and digit line 26. For a write operation to the selected MRAM cell 10, the control circuitry directs a write current through each of the appropriate bit and digit lines 28 and 26. A transistor 32, which may be a CMOS transistor, is connected by a conductive line 34 to the MTJ 12 to selectively isolate the MTJ 12 from the remainder of the circuitry. During a write operation, the transistor 32 is open to prevent the write current IW in the bit line 28 from flowing through the MTJ 12. During a read operation, however, the state of the transistor 32 is switched to closed so that the read current can flow through the MTJ 12.
Referring again to FIG. 1, the magnetic moment orientation 22 of the free layer 16 is represented as a single vector with a unique direction. While the direction of the magnetic moment within the free layer 16 generally has the orientation 22, near the edges of the free layer 16 the magnetic spins tend to curl away from the orientation 22 due to a demagnetization field. As noted above, when the two magnetic moment orientations 20 and 22 are parallel the resistance measured across the MTJ 12 is relatively low, and when the two magnetic moment orientations 20 and 22 are antiparallel the resistance measured across the MTJ 12 is relatively high. However, the curling effect tends to decrease the relatively high resistance and to increase the relatively low resistance such that the difference between the two states is reduced. Further, the curling effect is a dynamic effect and varies over time, causing the resistance across the MTJ 12 to continually vary in either the high or low resistance states. Thus, the reproducibility of the signal amplitude, the voltage measured across the MTJ 12, is reduced by the curling effect. The curling effect and its influence on reproducibility are also exacerbated by high temperatures and stray magnetic fields, making the MRAM cell 10 less stable and more likely to switch states unintentionally.
U.S. Pat. No. 6,174,737 B1 issued to Durlam et al., discloses an MRAM having a bit line, a magnetic memory element, and an electrically conductive layer disposed between the bit line and the magnetic memory element. Durlam et al. also discloses a Permalloy field focusing layer used in conjunction with both bit and digit lines. Durlam et al. does not explain specifically how a field focusing layer functions, except to say that a field focusing layer xe2x80x9cfacilitates magnetic fields to concentrate on the magnetic memory element.xe2x80x9d It is surmised that the term xe2x80x9cfield focusingxe2x80x9d is meant to imply that the layer serves to bend, reflect, or otherwise focus the magnetic field generated by the bit line or digit line in the direction of the magnetic memory element. Accordingly, Durlam et al. does not interpose a Permalloy layer between the digit or bit lines and the magnetic memory element because such a layer would tend to block the focusing effect and deflect the magnetic field away from the magnetic memory element.
Accordingly, what is desired is an improved design for an MRAM cell that reduces the curling effect within the free layer for increased stability. SUMMARY
An MRAM cell includes a magnetic tunneling junction, a bit line, and a digit line. The magnetic tunneling junction includes a free layer, a pinned layer, and a spacer layer disposed between them. The digit line includes a segment that is proximate to the pinned layer. The bit line includes a segment in electrical contact with the free layer. The MRAM cell also includes a magnetic liner layer disposed around the bit line segment and contacting the free layer. In some embodiments the magnetic liner layer together with the free layer form a sheath around the bit line segment. Because the sheath is a closed circuit formed of a magnetic material, a magnetic loop can encircle the bit line segment. The magnetic loop takes on the same orientation as the magnetic moment orientation of the free layer and eliminates the curling effect. In other embodiments the magnetic liner layer forms the entire sheath around the bit line segment. In these embodiments the liner layer contacts and is magnetically coupled to the free layer so that the magnetic loop takes on the same orientation as the magnetic moment orientation of the free layer. In additional embodiments the magnetic liner layer is electrically conductive so that it may carry a portion of the write current or the read current through the bit line segment.
Providing a magnetic loop around the digit line at the location of the magnetic tunnel junction creates several advantages. A first advantage is increased stability at elevated temperatures and in the presence of stray magnetic fields due to a reduction in the curling effect within the free layer. A second advantage is a reduction in power consumption. Power consumption is cut by the invention because the magnetic field from the digit line is concentrated at the free layer by the liner layer, thus reducing the amount of current necessary to produce a sufficient field at the free layer.
A method of fabricating an MRAM cell includes forming a digit line on a substrate and forming an insulating spacer including a contact via over the digit line. The digit line may be formed by patterning an oxide layer, filling the patterned lines with a conductive metal, and planarizing the top surface. The method of fabricating an MRAM cell further includes forming a bottom lead over the insulating spacer, which also may be achieved by patterning. The contact via in the insulating spacer allows the bottom lead to be electrically connected to an underlying CMOS transistor.
The method of fabricating an MRAM cell further includes forming a magnetic tunnel junction stack over the bottom lead. Forming the magnetic tunnel junction stack can include forming a first ferromagnetic layer over the bottom lead, forming a tunneling barrier layer over the first ferromagnetic layer, and forming a second ferromagnetic layer over the tunneling barrier layer. Forming the magnetic tunnel junction stack can also include forming an antiferromagnetic layer above the second ferromagnetic layer or forming the antiferromagnetic layer between the first ferromagnetic layer and the bottom lead. When the magnetic liner layer forms the entire sheath around the bit line segment, the antiferromagnetic layer should be formed between the first ferromagnetic layer and the bottom lead.
The method of fabricating an MRAM cell may also include forming an insulating material layer around the magnetic tunnel junction stack, and forming a silicon dioxide layer over the insulating material layer and over the magnetic tunnel junction stack. A trench with sidewalls can be formed in the silicon dioxide layer over the magnetic tunnel junction stack.
The method of fabricating an MRAM cell additionally includes forming a first liner layer over the magnetic tunnel junction, forming a bit line over the magnetic tunnel junction stack, and forming a second liner layer over the bit line. In some embodiments the liner layer is only formed on the sidewalls of the trench in order to produce a device in which three sides of a sheath around a bit line segment is formed by the magnetic liner layer and a fourth side of the sheath is formed by the free layer of the magnetic tunnel junction stack. In other embodiments the liner layer is also formed on the bottom of the trench and above the free layer to produce a device in which the sheath around the digit line segment is formed entirely by the magnetic liner layer. Forming the digit line can include plating a conductive metal over a seed layer to completely fill the trench, followed by a planarization. Forming a second liner layer over the digit line can also include forming and patterning a mask to allow the selective removal of the layer except over the bit line segment where it completes the sheath.